MIL-DTL-24784 / 21B (SH)
(3)
(3)
INPUT
SIGNAL
NAME
(2)
(2)
BIT 5*
BIT 4
SR-8
SR-8
(2)
(2)
(1)
(b)
(a)
ADDRESS
HIGHWAY SIGNAL NAME
INTERFACE REG SET OUTPUT
*
ANY REFERENCE IN TEXT OR TABLES TO THE
HIGHWAY INPUT SIGNAL MUST READ INTERFACE
BIT 6*
BIT 9
REG SET OUTPUT BIT 5.
SR-8
SR-8
(c)
*
ANY REFERENCE IN TEXT OR TABLES TO THE
HIGHWAY OUTPUT SIGNAL NAME MUST READ
ADDRESS BIT 6.
DATA
BIT 4 10
BIT 4 10
BIT 5 16
11 BIT 16
11 BIT 24
17 BIT 22
12 BIT 15
S-REG
S-REG
S-REG
PDL-A1
PDL-A1
PDL-A1
12 BIT 23
18 BIT 19
A2C27
A2C28
A2C29
13 BIT 14
13 BIT 22
19 BIT 18
14 BIT 13
20 BIT 17
14 BIT 21
16
16
21
CLOCK
TEST
BITS
NOTE: DOT CONNECTIONS USED
(d)
ON FCD FOR
ELECTRICALLY COMMON
CONNECTIONS.
CYL ADDRESS
BIT
0 12-6A
BIT
1 11-8B
X REG SET OUTPUT
BITS
1-5
5-3B
BIT
8
8-3A
(e)
FIGURE 21-13. Interconnecting lines. Example)
49
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